A new quantum computing standard has been proposed by NIST, focusing on gateless P-N junction metrology. The standard describes a specialized junction member with a p-interface and an adjacent n-interface, forming a p-n junction at their contact point. Drain and source electrodes are positioned on the junction member, with n- and p-polymer layers disposed on the respective interfaces. A mediation polymer layer is placed on top of the p-polymer, containing a mediator that receives electrons from the junction member to form the p-interface.
The proposed standard also includes a process for resistance metrology using the gateless P-N junction metrology. This involves connecting a first electrode to the p-interface and a second electrode to the n-interface, applying voltage across the drain and source electrodes, and measuring the resistance across the p-n junction using the first and second electrodes.
The potential impact of this standard could be significant for quantum technologies, as it provides a new method for resistance metrology in quantum devices. However, the implementation timeframes and technical details are not specified in the article.
Source: https://www.nist.gov/patents/gateless-p-n-junction-metrolog
Keywords: junction, metrolog, polymer
