NIST researchers have developed a new method called quantitative hybrid metrology (QHM) that integrates measurements from multiple instruments to more accurately determine the sizes of nanoscale transistor features on semiconductor chips. The method, which combines statistical techniques with measurements from scanning electron microscopes and optical devices, can reduce measurement uncertainty by more than a factor of three in some cases.
The NIST team, led by physicists Bryan Barnes and Richard Silver and statistician Nien Fan Zhang, estimates that a three-fold decrease in measurement uncertainty achievable with their innovation could save manufacturers as much as $7 for each chip they produce. Several companies and organizations, including IBM, GlobalFoundries, the University of California Berkeley, and Sematech, are adopting hybrid metrology, with important advances in their implementations since the inventors first introduced the statistical foundations to quantitative hybrid metrology.
The new method has the potential to be a cost-effective solution to an imposing challenge facing high-volume semiconductor manufacturers as dimensions decrease below 20 nanometers (nm). By 2019, transistor dimensions are slated to shrink to 10.9 nm. At present, there are no known solutions for measuring critical dimensions of that scale on chips, according to the International Technology Roadmap for Semiconductors.
Source: https://www.nist.gov/news-events/news/2013/07/nist-chip-measurement-advance-earns-oscar-innovation
Keywords: Metrology, Semiconductors, Nanoscale, Transistors, Accuracy
