Researchers at NIST, in collaboration with the U.S. government’s IARPA program, have developed a prototype nanoscale memory device designed for superconducting computers. While not yet an official industry standard, the project is actively establishing measurement and testing protocols that could eventually shape future hardware benchmarks. The technology is currently in the demonstration and evaluation phase, with NIST leading efforts to characterize its performance and lay the groundwork for standardized testing of next-generation computing components.
The memory device stores binary data by aligning internal magnetic layers either parallel or opposite, controlled simply through electrical currents instead of external magnets. Built at a nanoscale size, it operates at ultra-cold temperatures required by superconducting circuits, switches states hundreds of billions of times per second, and retains information without needing constant power refreshes. By solving the longstanding challenge of reliable cryogenic memory, this hybrid design could dramatically lower the massive electricity and cooling demands of modern data centers while enabling faster, more efficient processing.
Development is progressing through a multi-year government research initiative, with NIST experts projecting that fully integrated superconducting processors and memory systems could reach practical deployment within the next decade. If successful, this technology could serve as a foundational building block for ultra-low-power computing infrastructure, ultimately helping to establish new performance, reliability, and energy-efficiency standards across the global computing industry.
Source: https://www.nist.gov/news-events/news/2015/01/hybrid-memory-device-superconducting-computing
Keywords: superconducting computing, Josephson junctions, spintronic memory
